Explainers · RISC-V
RISC-V Inside Qwen 3.5 Weights: How Gated DeltaNet Became RAM for the Processor
On October 29, 2026, Habr published a translation of an analysis of Qwenputer: a 32-bit RISC-V is compiled into the weights of Qwen 3.5 4B, and its RAM is served by Gated DeltaNet layers. We examine the mechanics, checks, and boundaries of the experiment.
30 Oct 2026
6 min read
