RISC-V Inside Qwen 3.5 Weights: How Gated DeltaNet Became RAM for the Processor

On October 29, 2026, a translation of Divyansh Agrawal's article about Qwenputer appeared on Habr. This is Qwen 3.5 4B, with a 32-bit RISC-V processor compiled into its weights, and the model's own attention layers serve as its RAM. Below is what exactly was assembled, why the attention layers worked as memory, and how it was checked.

What Lies in the Weights

Qwenputer is an ordinary Qwen 3.5 4B plus one object inside the weights: a 32-bit RISC-V processor. RISC-V (an open instruction set; the core specification is available to everyone) in the RV32IM variant: 32-bit registers, the base integer set, and the M extension — multiplication and division. This is not silicon: the logic is compiled into the weights.

The processor occupies 11 layers before 32 layers of Qwen. After that come the model's standard layers. Computation happens inside forward passes (a normal pass of the model from input to output, the same as during text generation). There is no external execution environment.

The author separately stipulates: this is not a plugin, not a tool, and not a sandbox. The difference is practical. A tool is "called" by the model: it forms a request, and a separate program executes it. Here execution happens in the same matrices as a normal pass.

An example that helps keep the difference: when a model computes something through a code call, another process stands between it and the answer. In Qwenputer nothing stands between them — only the weights.

The model can be downloaded from Hugging Face or ModelScope, the code is on GitHub. There is no data on file sizes and hardware requirements in the source. The original's reading time is 7 minutes, Habr reach is 4.1K.

Why Gated DeltaNet Layers Are Suitable for the Role of RAM

In Qwen3-Next and Qwen 3.5, three out of four attention layers use Gated DeltaNet, abbreviated GDN — a linear RNN (a recurrent network whose processing cost grows linearly with sequence length rather than quadratically). Each head holds a state matrix; the delta rule updates it.

The author's observation: if you set the gate to 1, the write strength beta to 1, and encode keys as one-hot (a vector where exactly one component is equal to one and the rest are zeros), the behavior becomes predictable. A write overwrites exactly one row of the state. A query, also one-hot, returns the exact value from that row.

The mechanics are simple. The gate is a coefficient that decides how much of the old state survives the update; at one there is no decay. Beta is the write strength: how much of the new value enters the state. A one-hot key turns a write into addressing: a one stands at one position, and only the row with that number is updated.

Example: a key with a one in position 5 writes to row 5. A query with a one in position 5 reads row 5. Neighboring rows are not affected; there is no blurring.

Caveat: this is a mode of using the layers, not a claim that the model was originally designed as memory. The author tunes the parameters for his task — the gate and beta here are knobs, not properties of the architecture.

How It Was Checked That This Is a Processor

The check is the official riscv-tests, a set of tests for compliance with the RISC-V specification. The wording "passes riscv-tests" is present in the source. Exactly how many tests and with what result — there is no data.

Next — code execution. The model executes programs in C and in MicroPython (a stripped-down implementation of Python for microcontrollers) inside forward passes, without external tools. The interpreter also goes through the weights.

Example: to execute a loop in C, the model does not need a compiler nearby. It needs only its own forward pass.

What is not in the source: execution speed, comparison with a regular interpreter, limits on program size, energy consumption. These numbers are not there, and they should not be invented. "Passes tests" and "runs fast" are different statements.

What Is Nearby and What Is Not in the Text

The author attached an experimental file storage directly inside the model to Qwenputer. How it is structured — is not described in the given fragment; there is no data.

Two more texts by the author: about how hybrid models can learn to hide reasoning in an RNN state and bypass chain-of-thought monitoring, and about how compiled weights can serve as built-in monitoring tools that the model itself cannot interfere with. These are adjacent topics, not evidence.

It does not follow from the fact that the processor works in the weights that the model became faster or cheaper: there are no measurements. Numbers like "11 layers" and "4B" are a description of the configuration, not an assessment of quality. There is also no comparison of Qwenputer with regular Qwen 3.5 on benchmarks in the source.

What to Do with This

• Read it as an experiment about the expressiveness of weights, not as a product. No practical application is claimed in the text.
• Look at riscv-tests as a check of specification compliance, not as proof of performance.
• Check it yourself: the model on Hugging Face and ModelScope, the code on GitHub — the sources are available.
• Separate GDN into its own topic. State as memory, gate and beta as knobs — this is a technique that lives separately from Qwenputer.
• Keep the boundaries in mind: there is no data on speed, capacity, or price.